Title :
A high-speed dynamically reconfigurable 32-bit CMOS adder
Author :
Hwang, Inseok S. ; Magarschack, P.S.
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
A high-speed, compact three-way dynamically reconfigurable 32-bit CMOS adder is reported. The design of this adder uses an enhanced organization for 32-bit carry lookahead and uses an area-speed efficient dynamic circuit technique, called multiple-output domino logic. The reconfigurability is achieved without significant overhead on the basis of these combined techniques. The 248×1454-μm2 adder, fabricated in a standard 0.9-μm two-level metal CMOS technology, has demonstrated 32-bit addition times of 8.0 ns at 25°C with VDD=5.0 V
Keywords :
CMOS integrated circuits; adders; carry logic; digital arithmetic; integrated logic circuits; 0.9 micron; 32 bit; 32-bit carry lookahead; 5 V; 8 ns; CMOS adder; area-speed efficient dynamic circuit technique; high-speed; multiple-output domino logic; three-way dynamically reconfigurable; two-level metal CMOS technology; Adders; CMOS logic circuits; CMOS technology; Circuit stability; Logic circuits; Logic design; Logic devices; Logic functions; Logic gates; Reconfigurable logic;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20888
