PRAM process technology

Author

Koh, G.H. ; Hwang, Y.N. ; Lee, S.-H. ; Lee, S.Y. ; Ryoo, K.C. ; Park, J.H. ; Song, Y.J. ; Ahn, S.J. ; Jeong, C.W. ; Yeung, F. ; Kim, Y.T. ; Park, J.B. ; Jeong, G.T. ; Jeong, H.S. ; Kim, Kinam

Author_Institution

Adv. Technol. Dev. Team, Samsung Electron. Co., Ltd., South Korea

fYear

2004

fDate

2004

Firstpage

53

Lastpage

57

Abstract

PRAM(Phase-Change RAM) is a promising memory that can solve the problems of conventional memory and has the nearly ideal memory characteristics. We reviewed the issues for high density PRAM integration. Writing current reduction is the most urgent problem for high density PRAM realization. We presented process factors which affect the writing current and the result of improvement. Finally we demonstrated results of 64Mb PRAM integration based on 0.18μm CMOS technology.

Keywords

CMOS memory circuits; chalcogenide glasses; integrated circuit reliability; random-access storage; 64 Mbit; CMOS technology; advanced lithography; cell size scaling; chalcogenide material; endurance test; high density integration; nearly ideal memory characteristics; nonvolatility; phase-change RAM process technology; reliability; reversible phase change; scalability; writing current reduction; Amorphous materials; CMOS technology; Costs; Flash memory; Phase change materials; Phase change random access memory; Random access memory; Read-write memory; Switches; Writing;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309906

Filename

1309906