Title :
Advanced SOI substrate manufacturing
Author :
Mazur, C. ; Celler, G.K. ; Maleville, C. ; Cayrefourcq, I.
Author_Institution :
Soitec SA, Crolles, France
Abstract :
300 mm SOI wafers with sub-100nm thick active Si layers are currently produced in large quantities and used in advanced microprocessor circuits. To further enhance the performance of the next generation of devices, strained Si layers on insulator are being developed. The lattice mismatch between silicon and SiGe alloys, combined with layer transfer through the Smart Cut™ technology allow forming two types of strained Si - strained Si on SiGe on insulator, known as SGOI, and strained Si directly on insulator, known as sSOI. Fabrication methods and wafer characteristics for SOI, SGOI, and sSOI are discussed here.
Keywords :
CMOS integrated circuits; etching; ion implantation; oxidation; semiconductor superlattices; silicon-on-insulator; substrates; surface cleaning; wafer bonding; SOI wafers; Si; Si-SiGe; Smart Cut technology; advanced SOI substrate manufacturing; film thickness uniformity; high performance CMOS applications; ion implantation induced weakening; lattice mismatch; layer transfer; next generation devices; oxidation; selective wet etch; strained layers; ultrathin wafers; wafer bonding; wafer characteristics; wet cleaning; Circuits; Fabrication; Germanium silicon alloys; Insulation; Lattices; Manufacturing; Microprocessors; Silicon alloys; Silicon germanium; Silicon on insulator technology;
Conference_Titel :
Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on
Print_ISBN :
0-7803-8528-4
DOI :
10.1109/ICICDT.2004.1309919