Title :
A PIM-based multiprocessor system
Author :
Suh, Jinwoo ; Li, Changping ; Crago, Stephen P. ; Parker, Robert
Author_Institution :
Inf. Sci. Inst., Univ. of Southern California, Arlington, VA, USA
Abstract :
The growing gap in performance between processor and memory speeds has created a problem for data-intensive applications. A recent approach for solving this problem is to use processor-in-memory (PIM) technology. PIM technology integrates a processor on a DRAM memory chip, which increases bandwidth between the processor and memory. In this paper, we discuss a PIM-based multiprocessor system, the System Level Intelligent Intensive Computing (SLIIC) Quick look (QL) board. This system includes eight COTS PIM chips and two FPGA chips that implement a flexible interconnect network. The performance of the SLIIC QL board is measured and analyzed for the distributed corner-turn application. We show that the performance of the current SLIIC QL on the distributed corner turn application is better than a PowerPC-based multicomputer that consumes more power and occupies more area. This advantage, which can be achieved in a limited context, demonstrates that even limited COTS PIMs have some advantages for data-intensive computations
Keywords :
DRAM chips; field programmable gate arrays; multiprocessing systems; performance evaluation; DRAM memory chip; FPGA chips; PIM-based multiprocessor system; flexible interconnect network; memory speeds; performance; processor speeds; processor-in-memory technology; quick look board; system level intelligent intensive computing; Bandwidth; Delay; Field programmable gate arrays; Government; Multiprocessing systems; Performance analysis; Power system interconnection; Prefetching; Semiconductor device measurement; Utility programs;
Conference_Titel :
Parallel and Distributed Processing Symposium., Proceedings 15th International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-0990-8
DOI :
10.1109/IPDPS.2001.924932