Drowsy cache partitioning for reduced static and dynamic energy in the cache hierarchy

Power consumption is a major concern in today´s processor design. As technology shrinks, leakage power dominates the overall power consumption of the processor although it is expected that dynamic power gains relevance in future semiconductor technology. This is particularly relevant for the cache hierarchy, which contains an important percentage of the microprocessor transistors. In this work we propose the use of a phase adaptive cache design to reduce both leakage and dynamic power consumption with very little impact on the overall performance. We take advantage of the overwhelming preference of the memory accesses for the most recently used blocks, and the fact that these blocks are placed in a fast A partition of the cache. On the other hand, a B partition of the cache memory is placed in a drowsy mode in order to reduce the leakage power consumption of an important portion of the whole storage capacity. We test our design on a private second level cache reaching average dynamic energy savings almost 20% of the conventional cache design´s dynamic energy, and leakage energy savings close to 45% of the conventional cache design´s leakage energy. These results were achieved with minimal performance losses that stay within 2% of the original values.