Title :
A 100 MHz pipelined CMOS comparator for flash A/D conversion
Author :
Wu, Jieh-Tsorng ; Wooley, Bruce A.
Author_Institution :
Center for Integrated Syst., Stanford Univ., CA, USA
Abstract :
A description is given of the design of a VLSI-compatible CMOS comparator wherein voltage comparisons are accomplished directly by means of regenerative sensing. Input sampling, offset correction and common-mode cancellation have been incorporated into a pipelined cascade of regenerative sense amplifiers. Integrated in a standard 2-μm CMOS technology, the comparator operates at a maximum sampling rate of over 100 MHz, while dissipating only 3.6 mW of power from a single +5-V supply
Keywords :
CMOS integrated circuits; analogue-digital conversion; comparators (circuits); pipeline processing; 100 MHz; 2 micron; 3.6 mW; 5 V; ADC; VLSI-compatible; common-mode cancellation; flash A/D conversion; input sampling; maximum sampling rate; offset correction; pipelined CMOS comparator; regenerative sensing; sense amplifier cascade; single +5-V supply; standard 2-μm CMOS technology; voltage comparisons; CMOS technology; Circuits; Clocks; Data conversion; Delay estimation; Latches; Pipeline processing; Sampling methods; Switches; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20892
