Design aspects of a 4 Mbit 0.18 μm 1T1MTJ toggle MRAM memory

Author

Subramanian, Chitra K. ; Andre, Thomas W. ; Nahas, Joseph J. ; Garni, B.J. ; Lin, Halbert S. ; Omair, Ash ; Martino, William L., Jr.

Author_Institution

Motorola, Austin, TX, USA

fYear

2004

fDate

2004

Firstpage

177

Lastpage

181

Abstract

A 4 Mbit "Toggle" MRAM, built in 0.18 micron five level metal CMOS technology, using a 1.55 μm² bitcell with a single toggling magneto tunnel junction is described. The "Toggle" memory uses unidirectional programming currents controlled by switched local mirror circuits to achieve robust write operation. The isolated read architecture supports a 25 ns asynchronous cycle time operation, driven by balanced three input current mirror sense amplifiers.

Keywords

CMOS memory circuits; current mirrors; integrated circuit design; integrated circuit testing; magnetic tunnelling; magnetoresistive devices; microprogramming; random-access storage; 0.18 micron; 25 ns; 4 Mbit; asynchronous cycle time operation; balanced three input current mirror sense amplifiers; five level metal CMOS technology; isolated read architecture; magnetoresistance; magnetoresistive random access memory; robust write operation; single toggling magneto tunnel junction; switched local mirror circuits; toggle MRAM memory; unidirectional programming currents; Ash; CMOS technology; Conductors; Integrated circuit interconnections; Isolation technology; Magnetic tunneling; Memory architecture; Mirrors; Random access memory; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuit Design and Technology, 2004. ICICDT '04. International Conference on

Print_ISBN

0-7803-8528-4

Type

conf

DOI

10.1109/ICICDT.2004.1309940

Filename

1309940