Title :
Minimizing completion time for loop tiling with computation and communication overlapping
Author :
Goumas, Georgios ; Sotiropoulos, Aristidis ; Koziris, Nectarios
Author_Institution :
Dept. of Electr. Eng., Nat. Tech. Univ. of Athens, Greece
Abstract :
This paper proposes a new method for the problem of minimizing the execution time of nested for-loops using a tiling transformation. In our approach, we are interested not only in tile size and shape according to the required communication to computation ratio, but also in overall completion time. We select a time hyperplane to execute different tiles much more efficiently by exploiting the inherent overlapping between communication and computation phases among successive, atomic tile executions. We assign tiles to processors according to the tile space boundaries thus considering the iteration space bounds. Our schedule considerably reduces overall completion time under the assumption that some part from every communication phase can be efficiently overlapped with atomic, pure tile computations. The overall schedule resembles a pipelined datapath where computations are not anymore interleaved with sends and receives to non-local processors. Experimental results in a cluster of Pentiums by using various MPI send primitives show that the total completion time is significantly reduced
Keywords :
communication complexity; message passing; parallel algorithms; communication overlapping; hyperplanes; loop tiling; pipelined datapath; supernodes; tiling transformation; Automatic control; Delay; Laboratories; Parallel architectures; Parallel processing; Processor scheduling; Shape; Systems engineering and theory; Tiles; Vectors;
Conference_Titel :
Parallel and Distributed Processing Symposium., Proceedings 15th International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7695-0990-8
DOI :
10.1109/IPDPS.2001.924976