Analog maximum, median and minimum circuit

Author

Liu, Shen-Iuan ; Chen, Poki ; Chen, Chin-Yang ; Hwu, Jenn-Gwo

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

1

fYear

1997

fDate

9-12 Jun 1997

Firstpage

257

Abstract

In this paper, we present a new analog maximum, median and minimum circuit with a new preamplifier. This circuit can be used for sorting multiple-input analog signals. The median circuit has been implemented in a 0.8 μm single-poly double-metal (SPDM) CMOS process. The measured output error of this median circuit is less than 2.5 mV. Its frequency response can be up to 1 MHz. The maximum and minimum circuit are also verified by simulation. The experimental and simulation results confirm with the theoretical analysis

Keywords

CMOS analogue integrated circuits; analogue processing circuits; frequency response; median filters; preamplifiers; signal processing; 0.8 micron; 1 MHz; analog maximum circuit; analog median circuit; analog minimum circuit; frequency response; multiple-input analog signals; output error; preamplifier; signals sorting; single-poly double-metal CMOS process; Analytical models; CMOS process; Circuit simulation; Diodes; Filters; Frequency response; MOSFETs; Preamplifiers; Sorting; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.608692

Filename

608692