DocumentCode
312547
Title
Design and implementation of high-performance CMOS D/A converter
Author
Tan, Nianxiong ; Cijvat, Ellie ; Tenhunen, Hannu
Author_Institution
Ericsson Components AB, Kista, Sweden
Volume
1
fYear
1997
fDate
9-12 Jun 1997
Firstpage
421
Abstract
In this paper we present the design and implementation of a high-performance digital-to-analog converter in a 3.3-V 0.6-um digital CMOS process. To reduce glitch energy and maintain speed and small chip area, we combine segmentation and binary weighting, as well as clock all the input data before driving bit switches and equalize the delay for all the circuit blocks. We also present a new layout style, which enhances matching and further reduces glitch energy. Measurement results are also included
Keywords
CMOS integrated circuits; analogue-digital conversion; circuit layout CAD; delays; integrated circuit layout; 0.6 micron; 3.3 V; CMOS D/A converter; binary weighting; bit switches; chip area; delay equalization; glitch energy; layout style; segmentation; speed; CMOS process; CMOS technology; Clocks; Decoding; Intermodulation distortion; Microelectronics; Switches; Switching circuits; Switching converters; Telecommunication switching;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.608757
Filename
608757
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