• DocumentCode
    312579
  • Title

    MPRA implementation of a 1-D decimation filter

  • Author

    Kulkarni, Niranjan ; Lenders, Patrick M.

  • Author_Institution
    Dept. of Math. Stat. & Comput. Sci., New England Univ., Armidale, NSW, Australia
  • Volume
    1
  • fYear
    1996
  • fDate
    26-29 Nov 1996
  • Firstpage
    237
  • Abstract
    The main objective of this work is to explore possible implementations of a given algorithm on a MPRA (multi-phase multi-rate array). We have used a 1-D decimation filter as an example. The method used is to transform (with unimodular matrices) the recurrence equations describing the MPRA. The main relevant parameter of interest is the delay to produce one datum. An attempt has also been made to discover the optimum implementation (i.e. the implementation with smallest delay to produce a datum with respect to our criteria) as well as implementations with delays equal to multiples of the optimum delay. These latter implementations may be of interest when cascading decimation filters
  • Keywords
    VLSI; delays; digital filters; filtering theory; matrix algebra; recursive filters; signal processing; systolic arrays; 1D decimation filter; MPRA implementation; VLSI processor arrays; decimation filters cascading; multiphase multirate array; optimum delay; recurrence equations; signal processing; systolic arrays; unimodular matrices; Australia; Clocks; Delay; Difference equations; Differential equations; Filters; Hardware; Phased arrays; Strontium; Systolic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications
  • Conference_Location
    Perth, WA
  • Print_ISBN
    0-7803-3679-8
  • Type

    conf

  • DOI
    10.1109/TENCON.1996.608803
  • Filename
    608803