Title :
An analog VLSI chip with asynchronous interface for auditory feature extraction
Author :
Kumar, Nagendra ; Himmelbauer, Wolfgang ; Cauwenberghs, Gert ; Andreou, Andreas G.
Author_Institution :
Center for Language & Speech Process., Johns Hopkins Univ., Baltimore, MD, USA
Abstract :
We describe the architecture and circuit implementation of an analog VLSI feature extraction chip that has an asynchronous digital interface and is designed to serve as an auditory based front-end for a digit recognition system. The single chip system encodes signal energies and zero crossing time intervals of frequency components in a cochlear filter bank. The chip has been fabricated in a 1.2 μm n-well, double polysilicon, double metal CMOS process and it is fully functional. Power consumption when operated from a 5 V supply is only a few milliwatts
Keywords :
CMOS analogue integrated circuits; VLSI; analogue processing circuits; feature extraction; neural chips; speech recognition; speech recognition equipment; 1.2 micron; 5 V; analog VLSI chip; asynchronous interface; auditory based front-end; auditory feature extraction; cochlear filter bank; digit recognition system; double metal CMOS process; double polysilicon process; feature extraction chip; frequency components; n-well CMOS process; zero crossing time intervals; Circuits; Feature extraction; Filter bank; Hardware; Hidden Markov models; Histograms; Speech coding; Speech processing; Speech recognition; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
DOI :
10.1109/ISCAS.1997.608808
