• DocumentCode
    312587
  • Title

    The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification

  • Author

    Lan, Jeng-Feng ; Wu, Chung-Yu

  • Author_Institution
    Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
  • Volume
    1
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    565
  • Abstract
    In this paper, a multi-chip expandable modified feedforward Hamming neural network for pattern classification is designed and implemented. In the proposed modified Hamming network, the outstar circuit is used to provide the on-chip learning capability. Moreover, the embedded ratio memory in the outstar circuit is used to store the learned pattern. The chips can be connected to form pattern, element, and pattern-and-element-mixed expansions. The experimental results have correctly verified the operation of multi-chip expansion and classification function. The contrast enhancement characteristic of the stored pattern in the 3-chip element expansion has also been observed
  • Keywords
    CMOS analogue integrated circuits; Hamming codes; learning (artificial intelligence); neural chips; pattern classification; analog CMOS; contrast enhancement characteristic; embedded ratio memory; expandable modified Hamming neural network; multi-chip design; on-chip learning; outstar circuit; pattern classification; pattern-and-element-mixed expansions; Buildings; Circuits; Laboratories; Network-on-a-chip; Neural networks; Neurons; Pattern classification; Pattern matching; Routing; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.608816
  • Filename
    608816