Architecture and design of a very fast real time delay insensitive asynchronous morphological processor in GaAs

Author

Montiel-Nelson, Juan A. ; Nooshabai, S.

Author_Institution

Centre for Appl. Microelectron., Campus Univ. de Tafira, Spain

Volume

1

fYear

1996

fDate

26-29 Nov 1996

Firstpage

363

Abstract

Delay insensitive asynchronous design techniques are employed to implement a mathematical morphology processor in GaAs. A modified version of the DCVSL family is introduced, in order to achieve ultra-fast data rates. Simulation of the architecture implementation in GaAs MESFET 0.6 μm Vitesse technology demonstrates the reliability of this ASIC system for high end image processing applications

Keywords

III-V semiconductors; MESFET integrated circuits; VLSI; application specific integrated circuits; asynchronous circuits; digital signal processing chips; field effect logic circuits; gallium arsenide; image processing; mathematical morphology; 0.6 micron; ASIC system; GaAs; III V semiconductor; MESFET; Vitesse technology; asynchronous morphological processor; delay insensitive asynchronous design; differential cascode voltage switch logic; direct coupled FET logic; image processing applications; processor architecture; reliability; very fast processor design; CMOS technology; Clocks; Delay effects; Gallium arsenide; Image processing; MESFETs; Morphology; Pixel; Synchronization; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON '96. Proceedings., 1996 IEEE TENCON. Digital Signal Processing Applications

Conference_Location

Perth, WA

Print_ISBN

0-7803-3679-8

Type

conf

DOI

10.1109/TENCON.1996.608842

Filename

608842