High performance systolic memory architecture with binary tree structure

This paper proposes a scalable memory architecture with systolic dataflow. We divided the entire memory into N×N sub-memory blocks and placed them onto a scaleable two dimensional array that has communication channels of a partial binary tree structure. The operating speed is not determined by the entire memory size but the access time of a single memory block element. This architecture is suitable for applications where high throughput and scalability are of major importance. The initial latency of this scalable memory architecture is N+3 clock cycles for an N×N memory array because of the three directional data flows in the systolic memory array. The 4k-bit sized prototype of this memory architecture was designed by full custom layout using six transistor static RAM cell with a die size of 657×157 mil² and 0.8-μm single poly and double metal CMOS technology. The clock speed is 13 ns, determined by worse case simulation results