Title :
Contriving of a novel BIST (built in self-test) digital combinational lock
Author :
Sengar, Jitendra Singh ; Ghosh, Sudip ; Shekhar, S. Raj ; Verma, Pulkit ; Sharma, Ritu
Abstract :
This paper presents the design of digital combinational lock by using Finite State Machine. The digital combinational lock presented in this paper is equipped with advanced features wherein the user can set the combination of his or her choice “n” number of times. The inclusion of built in self testing (BIST) capabilities in the present system helps user to determine the lock condition. The source code of the digital combinational lock has been written in Verilog HDL and the designing has been done in Xilinx ISE.
Keywords :
built-in self test; combinational circuits; finite state machines; hardware description languages; logic design; BIST; Verilog HDL; Xilinx ISE; built in self-test; digital combinational lock design; finite state machine; Automata; Built-in self-test; Generators; Hardware design languages; Random sequences; Registers; Security; BIST; Digital Combinational Lock; Finite State Machine; Random Sequence Generator; Security system; Verilog HDL;
Conference_Titel :
Computing, Communications and Networking Technologies (ICCCNT),2013 Fourth International Conference on
Conference_Location :
Tiruchengode
Print_ISBN :
978-1-4799-3925-1
DOI :
10.1109/ICCCNT.2013.6726738
