VSPEC: a declarative specification methodology for system requirements

Systems engineering of computer-based systems demands explicit representation of functional requirements as well as constraints at each level of design abstraction. However, traditional design representation languages such as VHDL and VERILOG do not support requirements representation independent from implementation. This work presents a axiomatic specification language designed to support requirements representation. VSPEC annotates VHDL entity structures supporting declarative specification of input preconditions, output postconditions and performance constraints as a part of the design representation. The declarative nature of the specification supports requirements definition independent of design representation.