DocumentCode :
312638
Title :
An ART1 microchip and its use in multi-ART1 systems
Author :
Serrano-Gotarredona, Teresa ; Linares-Barranco, Bernabé
Author_Institution :
Nat. Microelectron. Center, Seville, Spain
Volume :
1
fYear :
1997
fDate :
9-12 Jun 1997
Firstpage :
673
Abstract :
Recently, a real-time clustering microchip based on the ART1 algorithm has been reported. This chip was able to classify 100-bit input patterns into up to 18 categories. However, its high area consumption (1 cm2) caused a very poor yield (6%). In this paper, an improved prototype is presented. In this chip, a different approach has been used to implement the most area consuming elements. The new chip can cope with 50-bit input patterns and classify them into up to 10 categories. Its area is 15 times less than that of the first prototype and it exhibits a yield performance of 98%. Due to its higher robustness, multichip systems are easily assembled
Keywords :
ART neural nets; neural chips; pattern classification; ART1 algorithm; area consumption; microchip; multichip system; pattern classification; real-time clustering; yield; Assembly systems; Circuits; Clustering algorithms; Computer architecture; Costs; Engines; Fault tolerance; Microelectronics; Prototypes; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
Type :
conf
DOI :
10.1109/ISCAS.1997.608925
Filename :
608925
Link To Document :
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