Title :
DLM/TLM compatible 1.0 μm gate array with over 100 K usable gates
Author :
Kobayshi, T. ; Aoki, Takao ; Tanaka, Yasunori ; Nakahara, Moriya ; Itabashi, Yasushi ; Hamada, Eiji ; Kohyama, Susumu
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
A double-level metal/triple-level metal compatible large-scale channelless gate array, 173 K gates on a chip, has been developed by utilizing a 1.0-μm twin-well HC2MOS process and a novel planarization technique for multilevel metallization. Two-input NAND propagation delay time measures 400 ps and 350 ps for DLM and TLM, respectively. A novel place-and-route algorithm achieved 40-60% gate utilization for DLM, i.e. over 100 K gates usable. In the case of TLM, utilization goes up to 60-85%, and even higher with larger macros such as memory modules, reaching around 150 k gates
Keywords :
CMOS integrated circuits; VLSI; cellular arrays; integrated logic circuits; 1 micron; 350 to 400 ps; DLM/TLM compatible; VLSI; channelless array; double-level metal; gate array; multilevel metallization; place/route algorithm; planarization technique; propagation delay time; triple-level metal; twin-well HC2MOS process; Chip scale packaging; Design automation; Integrated circuit interconnections; Libraries; Logic circuits; Logic design; Logic devices; Macrocell networks; Routing; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20904
