VLSI implementation of a functional neural network

Author

Panagiotopoulos, Dimokritos A. ; Singh, Sanjeev K. ; Newcomb, Robert W.

Author_Institution

Dept. of Autom., Technol. Inst. of Thessaloniki, Greece

Volume

1

fYear

1997

fDate

9-12 Jun 1997

Firstpage

701

Abstract

The VLSI implementation of a two-hidden layer discretized functional artificial neural network (FANN) has been demonstrated. A chip-set has been defined that implements the FANN, while it allows for expandability in the number of its inputs and outputs, as well as the number of neurons and connections in each hidden layer. Use of current-mode circuitry has resulted in compact multiplication circuitry and efficient manipulation of summation. The components (multiplier, exponential amplifier, analog memory cell) of the FANN have been implemented successfully, through MOSIS, using BiCMOS technology

Keywords

BiCMOS analogue integrated circuits; VLSI; analogue multipliers; analogue storage; neural chips; BiCMOS technology; FANN; MOSIS; VLSI implementation; analog memory cell; current-mode circuitry; exponential amplifier; functional neural network; multiplication circuitry; summation; two-hidden layer discretized network; Analog memory; Artificial neural networks; Automation; Circuits; Neural networks; Neurons; Postal services; Signal processing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.608960

Filename

608960