VIOOL for hardware/software codesign

While searching for a methodology to allow the use of C++ as a universal design language, or UDL, while incorporating available VHDL implementations, it became clear that an object oriented design environment was needed. To facilitate this complex transition an environment called VHDL Interfacing Object-Oriented Languages (VIOOL) has been treated. VIOOL is a tool suite that allows the system designer (user) to model and simulate a complete system (i.e., hardware and software) in C++. VIOOL enables users to make tradeoffs in the hardware or software of a system based on performance information. The input to VIOOL is a hardware configuration (usually a processor model) described in VHDL, and the software written that is supposed to run on that hardware in C++. VIOOL is targeted towards application specific signal processor (ASSP) and digital signal processor (DSP) developers. Preliminary results show the feasibility of this approach.