A protection cache architecture for the multi-view memory model and its performance

This paper presents a supporting architecture for the multi-view memory model and investigates its performance. The multi-view memory model is intended to provide applications with the variable-sized access units that they require for optimal performance within a computer system. The supporting architecture provides for the addressability of the state information which is kept on each variable sized-access unit. It is also designed to provide applications with a choice of access control protocol on various memory regions. Caches are integral to the architectural design. They allow for on-the-fly access rights determination and also for the flexibility of protocol choices. The miss rates on the caches within the access control protection subsystem architecture are determined using synthetic traces as input. The emphasis in this study is not to determine how traditional factors such as cache size, degree of associativity and line size affect the miss rates, but is targeted at evaluating the effect that views and their definitions have on the performance. It is found that the protection cache miss rate vary according to the sites of the access units defined within the views and the number and ratio of the differently-sized access unit entries within the protection cache.