Co-evolving algorithm-to-hardware gateway system design in manageable IP networks

We address a co-evolving algorithm-to-hardware design and implementation where multiple evolvable units (hardware and software) can be realized in a single embedded traffic manager in a gateway system for manageable IP networks (Jun Kyun Choi et al., ITU-T Recommendation in Progress, Y.NGN-CMIP, 2004). Our proposal eliminates the necessity of providing physical and dedicated memory resources and switching fabrics for data-intensive processing and suggests a self-triggered and self-adaptive mechanism for handling multiple real-time service provisioning, the key feature of manageable IP networks. We define a structure called the generative virtual algorithm data structure (GVA DS) that makes up the soft memory design for fast processing in a traffic manager for the implementation of our algorithm-to-hardware system. Soft memory design is a new concept that utilizes existing physical memory to map large scale data-driven processing to pipelined architectures. The soft memory system executes transforms as the core computational units where algorithms for handling the entire data vector are processed. A scheme for soft memory design for flow-based lookups in a co-evolving component based traffic manager is shown in the context of generating the processing block in-situ from the processed data on the fly. Our design shows a practical genre for implementing co-evolving component based design in gateway architectures for the next generation network (NGN)