Title :
Step spacing effects on electromigration
Author_Institution :
AT&T Bell Lab., Allentown, PA, USA
Abstract :
Step spacing effects on electromigration in second-level runners of a two-level metal technology are investigated by stressing test structures with a wide range of spacing, of severe topography. Metal step coverage is affected by step spacing, and it is shown that regions with poor coverage (10, 20%) are particularly vulnerable to electromigration failure. When the interlevel dielectric processing is changed to improve step coverage, metal lifetimes do not increase to the extent expected. A new mode that occurs within a specific range of step spacing appears to dominate failure.<>
Keywords :
CMOS integrated circuits; VLSI; aluminium alloys; copper alloys; electromigration; failure analysis; integrated circuit technology; life testing; metallisation; silicon alloys; AlSiCu runners; CMOS process; electromigration; electromigration failure; interlevel dielectric processing; metal lifetimes; second-level runners; severe topography; step spacing; step spacing effects; test structure stressing; two-level metal technology; Aluminum alloys; CMOS process; Current density; Dielectrics; Electromigration; Etching; Metallization; Surfaces; Testing; Thickness control;
Conference_Titel :
Reliability Physics Symposium, 1990. 28th Annual Proceedings., International
Conference_Location :
New Orleans, LA, USA
DOI :
10.1109/RELPHY.1990.66055
