• DocumentCode
    3127079
  • Title

    0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

  • Author

    Hara, H. ; Sakurai, T. ; Noda, M. ; Nagamatsu, T. ; Kobayashi, S. ; Seta, K. ; Momose, H. ; Niitsu, Y. ; Miyakawa, H. ; Maeguchi, K. ; Watanabe, Y. ; Sano, F.

  • Author_Institution
    Toshiba Corp.
  • fYear
    1991
  • fDate
    13-15 Feb. 1991
  • Firstpage
    148
  • Lastpage
    307
  • Keywords
    BiCMOS integrated circuits; CADCAM; Computer aided manufacturing; Cutoff frequency; Delay; Random access memory; Read only memory; Read-write memory; Solid state circuits; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Print_ISBN
    0-87942-644-6
  • Type

    conf

  • DOI
    10.1109/ISSCC.1991.689103
  • Filename
    689103
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3127079