3127079

0.5/spl mu/m 2M-transistor BipnMOS Channelless Gate Array

Hara, H. ; Sakurai, T. ; Noda, M. ; Nagamatsu, T. ; Kobayashi, S. ; Seta, K. ; Momose, H. ; Niitsu, Y. ; Miyakawa, H. ; Maeguchi, K. ; Watanabe, Y. ; Sano, F.

Toshiba Corp.

1991

13-15 Feb. 1991

148

307

BiCMOS integrated circuits; CADCAM; Computer aided manufacturing; Cutoff frequency; Delay; Random access memory; Read only memory; Read-write memory; Solid state circuits; Voltage;

English

ieee

Solid-State Circuits Conference, 1991. Digest of Technical Papers. 38th ISSCC., 1991 IEEE International

San Francisco, CA, USA

0-87942-644-6

conf

10.1109/ISSCC.1991.689103

689103