Novel locally strained channel technique for high performance 55nm CMOS

Author

Ota, K. ; Sugihara, K. ; Sayama, H. ; Uchida, T. ; Oda, H. ; Eimori, T. ; Morimoto, H. ; Inoue, Yasuyuki

Author_Institution

ULS1 Dev. Center, Mitsubishi Electr. Corp., Hyogo, Japan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

27

Lastpage

30

Abstract

A novel local strained channel (LSC) MOSFET has been fabricated by a stress control technique utilizing a strained poly silicon gate electrode. The residual compressive stress in arsenic (As) implanted polysilicon is induced by high temperature annealing of CVD SiO/sub 2/ cap with high tensile stress. On the other hand, boron (B) implanted poly silicon is free from stress. As a result, the only n-channel region is locally strained by the strained polysilicon electrode. The drain current of LSC nFETs is improved 15% compared to that of the conventional nFET without the degradation of pFET drain current. High performance 55nm CMOSFET is realized by simple process for LSC-structure.

Keywords

Ge-Si alloys; MOSFET; annealing; arsenic; boron; elemental semiconductors; internal stresses; semiconductor materials; silicon; 55 nm; CMOSFET; LSC-structure; Si:As-SiGe; Si:B-SiGe; drain current; high temperature annealing; locally strained channel technique; n-channel region; residual compressive stress; strained polysilicon gate electrode; stress control technique; Annealing; Boron; Compressive stress; Electrodes; MOSFET circuits; Residual stresses; Silicon; Stress control; Temperature; Tensile stress;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175771

Filename

1175771