Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations

Author

Vazquez, Manuel ; Sutter, G. ; Bioul, G. ; Deschamps, J.P.

Author_Institution

UNCPBA Univ., Tandil, Argentina

fYear

2009

fDate

9-11 Dec. 2009

Firstpage

42

Lastpage

47

Abstract

This paper presents FPGA implementations of add/subtract algorithms for 10´s complement BCD numbers. Carry-chain type circuits have been designed on 6-input LUT´s Xilinx Virtex-5 FPGA technologies. Some new concepts are reviewed to compute the P and G functions for carry-chain optimization purposes. Designs are presented with the corresponding time performances and area consumption figures. Results have been compared with 2´s complement binary implementations carried out on the same platform. Better time delays have been registered for decimal number within same range of operands.

Keywords

adders; field programmable gate arrays; logic design; optimisation; BCD numbers; FPGA implementations; LUTs Xilinx Virtex-5 FPGA technology; area consumption figures; binary implementations; carry-chain optimization purposes; carry-chain type circuits; decimal adders; subtractors; time delays; time performances; Adders; Application software; Circuits; Data processing; Decoding; Delay effects; Digital arithmetic; Field programmable gate arrays; Hardware; Table lookup; BCD; FPGA; add/subtract; addtion; decimal arithmetic; subtraction;

fLanguage

English

Publisher

ieee

Conference_Titel

Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on

Conference_Location

Quintana Roo

Print_ISBN

978-1-4244-5293-4

Electronic_ISBN

978-0-7695-3917-1

Type

conf

DOI

10.1109/ReConFig.2009.29

Filename

5382025