Title :
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier
Author :
Minchola, Carlos ; Sutter, Gustavo
Author_Institution :
Sch. of Eng., Univ. Autonoma de Madrid, Madrid, Spain
Abstract :
This paper describes the design and implementation of a hardware module to calculate the decimal floating-point (DFP) multiplication compliant with the current IEEE-754-2008 standard. The design proposed is made up of independent stages: IEEE-754 coder / decoder, decimal multiplier and rounding. The decimal multiplication is based on a previously designed BCD multiplier. The novelty is the design of a combinational and sequential architecture for rounding stage. Time performances and hardware requirements results are reported and evaluated. A decimal64 multiplication is able to be performed in 66 ns in a Virtex 4. The DFP multiplication presented supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To the best of author´s knowledge, this is the first publication to present an IEEE 754-2008 multiplier in FPGA.
Keywords :
IEEE standards; binary codes; combinational circuits; decoding; field programmable gate arrays; floating point arithmetic; logic design; sequential circuits; BCD multiplier; FPGA; IEEE-754 coder; IEEE-754-2008 standard; Virtex 4; combinational architecture; decimal floating-point multiplication; decimal multiplier; decimal128 format; decimal64 multiplication; decoder; hardware module; hardware requirements; rounding; sequential architecture; time 66 ns; time performances; Application software; Decoding; Design engineering; Field programmable gate arrays; Floating-point arithmetic; Hardware; Manufacturing; Microprocessors; Performance evaluation; Standards development;
Conference_Titel :
Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on
Conference_Location :
Quintana Roo
Print_ISBN :
978-1-4244-5293-4
Electronic_ISBN :
978-0-7695-3917-1
DOI :
10.1109/ReConFig.2009.34