A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 /spl mu/m/sup 2/ SRAM cell

Author

Thompson, S. ; Anand, N. ; Armstrong, M. ; Auth, C. ; Arcot, B. ; Alavi, M. ; Bai, P. ; Bielefeld, J. ; Bigwood, R. ; Brandenburg, J. ; Buehler, M. ; Cea, S. ; Chikarmane, V. ; Choi, C. ; Frankovic, R. ; Ghani, T. ; Glass, G. ; Han, W. ; Hoffmann, T. ; Hu

Author_Institution

Intel Corp., Hillsboro, OR, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

61

Lastpage

64

Abstract

A leading edge 90 nm technology with 1.2 nm physical gate oxide, 50 nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k carbon-doped oxide (CDO) for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by >50%. Aggressive design rules and unlanded contacts offer a 1.0 /spl mu/m/sup 2/ 6-T SRAM cell using 193 nm lithography.

Keywords

CMOS logic circuits; CMOS memory circuits; SRAM chips; ULSI; copper; high-speed integrated circuits; hole mobility; integrated circuit interconnections; integrated circuit technology; nanoelectronics; nanolithography; silicon; ultraviolet lithography; 1.2 V; 1.2 nm; 193 nm; 2 GHz; 50 nm; 52 Mbit; 6-T SRAM cell; 90 nm; Cu; Cu interconnects; DUV lithography; NiSi; Si; SiO/sub 2/:C; carbon-doped oxide; high performance dense logic; logic technology; low k C-doped oxide; mobility; saturated NMOS drive currents; saturated PMOS drive currents; strained Si channel transistors; CMOS technology; Implants; Isolation technology; Lithography; Logic; MOS devices; MOSFETs; Microprocessors; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175779

Filename

1175779