A 90-nm CMOS device technology with high-speed, general-purpose, and low-leakage transistors for system on chip applications

Author

Wu, C.C. ; Leung, Y.K. ; Chang, C.S. ; Tsai, M.H. ; Huang, H.T. ; Lin, D.W. ; Sheu, Y.M. ; Hsieh, C.H. ; Liang, W.J. ; Han, L.K. ; Chen, W.M. ; Chang, S.Z. ; Wu, S.Y. ; Lin, S.S. ; Lin, H.C. ; Wang, C.H. ; Wang, P.W. ; Lee, T.L. ; Fu, C.Y. ; Chang, C.W. ;

Author_Institution

Taiwan Semicond. Manuf. Co., Taiwan

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

65

Lastpage

68

Abstract

A leading edge 90nm bulk CMOS device technology is described in this paper. In this technology, multi Vt and multi gate oxide devices are offered to support low standby power (LP), general-purpose (G or ASIC), and high-speed (HS) system on chip (SoC) applications. High voltage I/O devices are supported using 70/spl Aring/, 50/spl Aring/, and 28/spl Aring/ gate oxide for 3.3V, 2.5V, and 1.5-1.8V interfaces, respectively. The backend architecture is based on nine levels of Cu interconnect with hot black diamond (HBD) low-k dielectric (k<=3.0).

Keywords

CMOS digital integrated circuits; VLSI; high-speed integrated circuits; integrated circuit design; integrated circuit technology; leakage currents; low-power electronics; system-on-chip; 1.5 to 3.3 V; 28 to 70 angstrom; 90 nm; CMOS device technology; Cu; backend architecture; high voltage I/O devices; high-speed system on chip; hot black diamond; low-k dielectric; low-leakage transistors; multi gate oxide devices; standby power; system on chip applications; CMOS technology; Capacitance; Degradation; Delay; Dielectrics; Implants; Integrated circuit interconnections; Nickel; Random access memory; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175780

Filename

1175780