Author :
Kim, Y.W. ; Oh, C.B. ; Ko, Y.G. ; Lee, K.T. ; Ahn, J.H. ; Park, T.S. ; Kang, H.S. ; Lee, D.H. ; Jung, M.K. ; Yu, H.J. ; Jung, K.S. ; Liu, S.H. ; Oh, B.J. ; Kim, K.S. ; Lee, N.I. ; Park, M.H. ; Bae, G.J. ; Lee, S.G. ; Song, W.S. ; Wee, Y.G. ; Jeon, C.H. ;
Abstract :
A 90 nm generation logic technology with Cu/low-k interconnects is reported. 50 nm transistors are employed using gate oxide 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 /spl mu/A/pm and 360 /spl mu/A//spl mu/m for NMOS and PMOS respectively, while generic transistors have currents of 640 /spl mu/A//spl mu/m and 260 /spl mu/A//spl mu/m respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu/low-k interconnects. The effective k (k/sub eff/) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 /spl mu/m/sup 2/ and SNM value of 330 mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.
Keywords :
CMOS digital integrated circuits; MIM devices; SRAM chips; capacitance; dielectric thin films; integrated circuit interconnections; low-power electronics; silicon-on-insulator; system-on-chip; 1.0 V; 1.3 nm; 330 mV; 50 nm; 90 nm; Cu; Cu/low-k interconnects; MIM capacitor; SNM value; SOI process; SRAM cell; SoC applications; drive currents; dual damascene; gate length; high-k gate dielectrics; logic technology; low power process; voltage coefficient of capacitance; CMOS logic circuits; CMOS technology; Dielectric devices; High K dielectric materials; High-K gate dielectrics; Logic devices; Logic gates; MOS devices; Portfolios; System-on-a-chip;
