DocumentCode

3127724

Title

Minimizing routing configuration cost in dynamically reconfigurable FPGAs

Author

Rakhmatov, Daler ; Vrudhula, Sarma B K

Author_Institution

University of Arizona

fYear

2000

fDate

23-27 April 2000

Firstpage

1481

Lastpage

1488

Keywords

Character generation; Costs; Delay; Field programmable gate arrays; Hardware; Power dissipation; Reconfigurable logic; Routing; Runtime; Standards organizations;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Processing Symposium., Proceedings 15th International

Conference_Location

San Francisco, CA, USA

ISSN

1530-2075

Print_ISBN

0-7695-0990-8

Type

conf

DOI

10.1109/IPDPS.2001.925132

Filename

925132