DocumentCode
3128425
Title
High-Level FPGA Programming through Mapping Process Networks to FPGA Resources
Author
Mayer-Lindenberg, Fritz
Author_Institution
Inst. of Comput. Technol., Tech. Univ. of Hamburg-Harburg, Hamburg, Germany
fYear
2009
fDate
9-11 Dec. 2009
Firstpage
302
Lastpage
307
Abstract
We describe a simple and fast approach to FPGA programming that allows to efficiently exploit the numeric processing capabilities of recent FPGA chips. It basically consists in programming on top of a library of complex components for FPGA based scalable processor networks and providing a high-level programming interface to it. The FPGA application is presented as a network of processes which is automatically transformed into a corresponding network of simple processor components by a compiler. The compiler then generates individual program code for each of the simple processors. The coarse-grained processor network is eventually compiled into an FPGA configuration bitstream using standard FPGA tools at close-to-interactive speeds. Our approach has the additional benefit of being fully compatible with processor programming and extendible to mixed multi-component FPGA and processor systems. An experimental implementation of the process mapping scheme uses the p-Nets language that provides convenient structures for the presentation of the application processes and supports composite targets including processors linked to the FPGA chips. The evaluation of our concept on some FPGA chips includes an estimate of their floating point processing performances.
Keywords
codes; field programmable gate arrays; microprocessor chips; program compilers; FPGA based scalable processor networks; FPGA configuration bitstream; close-to-interactive speeds; coarse-grained processor network; floating point processing; high-level FPGA programming; high-level programming interface; mixed multicomponent FPGA; p-Nets language; process network mapping; program code; Arithmetic; Computer networks; Costs; Delay; Field programmable gate arrays; Hardware design languages; Integrated circuit interconnections; Libraries; Routing; SDRAM;
fLanguage
English
Publisher
ieee
Conference_Titel
Reconfigurable Computing and FPGAs, 2009. ReConFig '09. International Conference on
Conference_Location
Quintana Roo
Print_ISBN
978-1-4244-5293-4
Electronic_ISBN
978-0-7695-3917-1
Type
conf
DOI
10.1109/ReConFig.2009.73
Filename
5382069
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