Title :
USLI system models
Author :
De, Vivek K. ; Berger, Michael ; Meindl, James D.
Author_Institution :
Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
Generic system-level models for CMOS CPUs are discussed. A novel system-level model for CMOS static RAMs is introduced. These models are used to evaluate the impact of several critical chip and module technology parameters and architectural features on the single most important indicator os system performance, the system clock frequency. A methodology is developed for defining optimal levels of integration for CPU and memory systems
Keywords :
CMOS integrated circuits; VLSI; integrated circuit technology; integrated memory circuits; microprocessor chips; random-access storage; CMOS; CPUs; SRAM packaging technology; USLI system models; architectural features; chip parameters; critical parameters; module technology parameters; optimal levels of integration; partitioning; static RAMs; system clock frequency; system-level models; CMOS technology; Circuits; Clocks; Frequency; Logic; Microprocessors; Power system modeling; Predictive models; Semiconductor device modeling; Ultra large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20917
