DocumentCode
3128466
Title
Novel shallow trench isolation process using flowable oxide CVD for sub-100 nm DRAM
Author
Chung, Sung-Woong ; Ahn, Sang-Tae ; Sohn, Hyun-Chul ; Ku, Jachun ; Park, SungKi ; Song, Yong-wook ; Park, Hyo-Sik ; Lee, Sang-Don
Author_Institution
Memory R&D Div., Hynix Semicond. Inc., Kyoungki-do, South Korea
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
233
Lastpage
236
Abstract
We have investigated the characteristics of cell leakage and data retention time when using flowable oxide chemical vapor deposition (CVD) as a shallow trench isolation (STI) process of 1-Gbit DRAM. The trench gap filling capability was increased dramatically by combining high-density plasma (HDP) CVD with flowable oxide CVD. The reduced local stress by flowable oxide in narrow trenches leaded to decrease in junction leakage and gate induced drain leakage (GIDL) current and increase in data retention time of DRAM compared to HDP STI. Therefore, it is concluded that the combination of flowable oxide and HDP oxide is the most promising technology for STI gap filling process of sub-100 nm DRAM technology.
Keywords
CMOS memory circuits; DRAM chips; chemical vapour deposition; integrated circuit reliability; internal stresses; isolation technology; leakage currents; plasma CVD; 1 Gbit; 100 nm; DRAM reliability; SiO/sub 2/-Si; cell leakage; data retention time; flowable oxide CVD; flowable oxide chemical vapor deposition; gate induced drain leakage current; high-density plasma CVD; junction leakage current; reduced local stress; shallow trench isolation process; sub-100 nm DRAM; trench gap filling capability; Chemical vapor deposition; Cleaning; Facsimile; Filling; Isolation technology; Plasma chemistry; Random access memory; Research and development; Temperature; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175820
Filename
1175820
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