DocumentCode
3128855
Title
Line edge roughness: characterization, modeling and impact on device behavior
Author
Croon, J.A. ; Storms, G. ; Winkelmeier, S. ; Pollentier, I. ; Ercken, M. ; Decoutere, S. ; Sansen, Willy ; Maes, H.E.
Author_Institution
IMEC, Leuven, Belgium
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
307
Lastpage
310
Abstract
Simple analytical expressions are presented, which calculate the impact of line edge roughness on MOSFET parameter fluctuations. It is experimentally demonstrated that LER has no impact on 80 nm gate length transistors. Simulations show LER to become significant for 32 nm channel length devices.
Keywords
MOSFET; fluctuations; semiconductor device measurement; semiconductor device models; surface topography; ultraviolet lithography; 193 nm; 193 nm lithography process; 32 nm; 32 nm channel length devices; 80 nm; 80 nm gate length transistors; MOSFET; MOSFET parameter fluctuations; analytical expressions; characterization; device behavior; line edge roughness; modeling; simulations; top-view SEM image; Analytical models; Degradation; Fluctuations; Frequency conversion; Lithography; MOSFET circuits; Predictive models; Sampling methods; Scanning electron microscopy; Storms;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175840
Filename
1175840
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