Optimal global interconnecting devices for GSI

Author

Naeemi, A. ; Davis, J.A. ; Meindl, J.D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

319

Lastpage

322

Abstract

Size of global interconnects is optimized to have a large bisectional bandwidth as well as small latency. Using physical models it is shown that by maximizing the bandwidth-reciprocal latency product, the delay variation due to different switching patterns decreases to less than 3%. The required silicon area for global repeaters is also less than 1% of the chip area. Compact physical models are derived for far inductive noise, which show that noise remains small and constant (less than 0.2 V/sub dd/) for all technology generations if optimal wire width is used.

Keywords

SPICE; circuit optimisation; circuit simulation; crosstalk; delay estimation; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; GSI; HSPICE simulations; bandwidth-reciprocal latency product; bisectional bandwidth; chip area; compact physical models; crosstalk; delay variation; far inductive noise; global interconnect device optimization; global repeaters; long global interconnects; optimal wire width; physical models; silicon area; switching patterns; Bandwidth; Bit rate; Capacitance; Conductivity; Delay; Dielectric constant; Noise generators; Repeaters; Silicon; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175843

Filename

1175843