Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time

Large applications that exceed available FPGA resources must time-multiplex these resources using smaller hardware modules. In order to orchestrate this time-multiplexing, temporal partitioning partitions these hardware modules into multiple subsets, each of which fit within the available resources. During a temporal partition transition, the FPGA is reconfigured to the subsequent temporal partition. However, FPGA reconfiguration time can impose significant performance overhead as the entire FPGA fabric must be reconfigured even if only a small portion has changed. Partially reconfigurable (PR) FPGAs can decrease reconfiguration time by only reconfiguring the portions of the FPGA fabric that differ. In this paper, we present a design methodology using a simulated annealing-based module placement optimization engine to minimize FPGA reconfiguration overhead by exploiting module overlap across successive temporal partitions. Experimental results show that our methodology reduces FPGA reconfiguration time by 44% on average.