An 85–95.2 GHz transformer-based injection-locked frequency tripler in 65nm CMOS

A W-band transformer-based injection-locked frequency tripler (T-ILFT) is designed and implemented in 65 nm standard CMOS technology using a 0.8 V supply voltage. The use of injection locking topology with on-chip transformer provides several advantages over conventional design. Occupying an chip area of 0.089 mm² (including buffers), the T-ILFT achieves an input sensitivity of -15 dBm and a continuous locking range from 85 to 95.2 GHz with 4 dBm input power. The measured phase noise degradation from that of the input signal source is only 9.8dB at 1MHz offset. The harmonic suppressions for the first and second harmonics are measured to be 32.9 dB and 38.5 dB, respectively. The power consumption is only 5.2 mW for T-ILFT and 14.6 mW for output buffers. To the authors´ best knowledge, this T-ILFT achieves the highest operation frequency for injection-locked-based frequency multipliers, reported to date.