Tunable work function dual metal gate technology for bulk and non-bulk CMOS

Author

Lee, Jaehoon ; Zhong, Huicai ; Suh, You-Seok ; Heuss, Greg ; Gurganus, Jason ; Chen, Bei ; Misra, Veena

Author_Institution

Dept. of Electr. Eng., North Carolina State Univ., Raleigh, NC, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

359

Lastpage

362

Abstract

This paper describes a metal gate process, which provides tunable work function values and ease of integration for dual metal gate process flow. Vertical stacks of Ru and Ta layers were subjected to high temperature anneals to promote intermixing which resulted in /spl phi//sub m/ tuning. It was found that Ru/Ta stacks provided up to 0.4 eV reduction in /spl phi//sub m/ compared to Ru. To increase this change, stacks of Ru/sub 50/Ta/sub 50//Ru were also evaluated and nearly a 0.8 eV change in /spl phi//sub m/ was observed between Ru/sub 50/Ta/sub 50//Ru and Ru/sub 50/Ta/sub 50/ electrodes.

Keywords

CMOS integrated circuits; MOS capacitors; chemical interdiffusion; integrated circuit metallisation; rapid thermal annealing; ruthenium; tantalum; work function; 10 sec; 30 sec; 500 to 1000 C; MOS capacitor fabrication process; Ru-Ta; Ru/Ta vertical stacks; Ru/sub 50/Ta/sub 50/-Ru; bulk CMOS; equivalent oxide thickness; high temperature anneals; intermixing; nonbulk CMOS; tunable work function dual metal gate technology; Annealing; CMOS technology; Capacitance-voltage characteristics; Channel bank filters; Electrodes; Fabrication; Fluctuations; MOS capacitors; Stability; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175852

Filename

1175852