Investigation of power distribution strategies for wafer scale integration (WSI)

Author

York, Trevor A.

Author_Institution

Dept. of Electr. Eng. & Electron., Univ. of Manchester Inst. of Sci & Technol., UK

fYear

1988

fDate

16-19 May 1988

Abstract

The problem of power distribution for WSI has been investigated, using SPICE simulations of distribution strategies for a number of wafer sizes under conditions of varying rail dimensions and processor size. Simulations concentrate on strategies used in an earlier, more specific report, involving grid arrangements in double-layer metal. Results support the suggestion that rails must be several hundred square micrometers in cross section to guarantee integrity of the supply. Large processors are seen to be only fractionally more attractive and a decision regarding this would therefore be dominated in practice by yield consideration. A prospective scheme is proposed which involves continuous metal surfaces for power and ground. This promises attractive performance if a practical realization is possible

Keywords

VLSI; integrated circuit technology; metallisation; SPICE simulations; WSI; continuous metal surfaces; cross sectional area; double-layer metal; grid arrangements; power distribution strategies; processor size; rail dimensions; wafer scale integration; wafer sizes; yield; Circuits; Current density; Degradation; Distribution strategy; Power distribution; Power supplies; Rails; SPICE; Voltage; Wafer scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988

Conference_Location

Rochester, NY

Type

conf

DOI

10.1109/CICC.1988.20923

Filename

20923