DocumentCode
3129453
Title
High performance 40 nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gate
Author
Tavel, B. ; Garros, X. ; Skotnicki, T. ; Martin, F. ; Leroux, C. ; Bensahel, D. ; Séméria, M.N. ; Morand, Y. ; Damlencourt, J.F. ; Descombes, S. ; Leverd, F. ; Le-Friec, Y. ; Leduc, P. ; Rivoire, M. ; Jullian, S. ; Pantel, R.
Author_Institution
France Telecom R&D, Meylan, France
fYear
2002
fDate
8-11 Dec. 2002
Firstpage
429
Lastpage
432
Abstract
We report on 40 nm nMOS transistors with HfO/sub 2/ dielectric and polySi gate integrated into a damascene structure. We fabricated HfO/sub 2/ ALD layers with EOT down to 15 /spl Aring/, exhibiting leakage current more than two decades lower than SiO/sub 2/. Small mobility degradation on 2 nm EOT nMOSFETs was observed leading to the best performances (Ion= 680 /spl mu/A//spl mu/m @ Ioff=230 nA//spl mu/m) ever obtained with HfO/sub 2/ and polySi electrodes.
Keywords
MOSFET; annealing; carrier mobility; dielectric thin films; hafnium compounds; leakage currents; 15 A; 40 nm; 40 nm nMOSFETs; EOT; HfO/sub 2/ ALD layers; HfO/sub 2/ gate dielectric; HfO/sub 2/-Si; damascene structure; leakage current; low temperature post-deposition annealing; mobility degradation; polysilicon damascene gate; Annealing; CMOS technology; Channel bank filters; Degradation; Electrodes; Etching; Hafnium oxide; High-K gate dielectrics; Leakage current; MOSFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7462-2
Type
conf
DOI
10.1109/IEDM.2002.1175870
Filename
1175870
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