A sub-400/spl deg/C germanium MOSFET technology with high-/spl kappa/ dielectric and metal gate

Author

Chi On Chui ; Hyoungsub Kim ; Chi, D. ; Triplett, B.B. ; McIntyre, P.C. ; Saraswat, K.C.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., CA, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

437

Lastpage

440

Abstract

A novel low thermal budget (/spl les/400/spl deg/C) germanium MOS process with high-/spl kappa/ gate dielectric and metal gate electrode has been demonstrated. For the first time, self-aligned surface-channel Ge p-MOSFETs with ZrO/sub 2/ gate dielectric having equivalent oxide thickness (EOT) of 6-10 /spl Aring/ and platinum gate electrode are demonstrated with twice the low-field hole mobility of Si MOSFETs.

Keywords

MOSFET; annealing; dielectric thin films; elemental semiconductors; germanium; hole mobility; ion implantation; semiconductor device metallisation; zirconium compounds; 400 C; 6 to 10 A; Pt gate electrode; Pt-ZrO/sub 2/-Ge; ZrO/sub 2/ gate dielectric; equivalent oxide thickness; high-/spl kappa/ gate dielectric; low thermal budget Ge MOSFET technology; low-field hole mobility; metal gate electrode; self-aligned surface-channel Ge p-MOSFETs; Annealing; Capacitance-voltage characteristics; Dielectrics; Electrodes; Germanium; MOS capacitors; MOSFET circuits; Optical surface waves; Surface cleaning; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175872

Filename

1175872