Title :
A 0.25/spl mu/m CMOS based 70V smart power technology with deep trench for high-voltage isolation
Author :
Parthasarathy, V. ; Zhu, R. ; Khemka, V. ; Roggenbauer, T. ; Bose, A. ; Hui, P. ; Rodriquez, P. ; Nivison, J. ; Collins, D. ; Wu, Z. ; Puchades, I. ; Butner, M.
Author_Institution :
Semicond. Products Sector, Motorola Inc, Tempe, AZ, USA
Abstract :
Presents a 0.25/spl mu/m CMOS based smart power platform on a P++ substrate with a deep trench high-voltage isolation as a low-cost alternative to SOI in realizing significant analog shrink, reduction of substrate parasitics and 70V high-side capability without affecting analog matching and process complexity.
Keywords :
CMOS integrated circuits; integrated circuit measurement; isolation technology; mixed analogue-digital integrated circuits; power integrated circuits; 0.25 micron; 70 V; CMOS; P++ substrate; analog matching; analog shrink; deep trench; high-side capability; high-voltage isolation; process complexity; smart power technology; substrate parasitics; CMOS logic circuits; CMOS process; CMOS technology; Implants; Isolation technology; Logic devices; Medium voltage; Silicon; Substrates; Thermal stresses;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175878
