DocumentCode
3129673
Title
Field-testing IMPACT EPIC research results in Itanium 2
Author
Sias, John W. ; Ueng, Sain-Zee ; Kent, Geoff A. ; Steiner, Ian M. ; Nystrom, Erik M. ; Hwu, Wen-Mei W.
Author_Institution
Dept. of Reliable & High-Performance Comput., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
fYear
2004
fDate
19-23 June 2004
Firstpage
26
Lastpage
37
Abstract
Explicitly-Parallel Instruction Computing (EPIC) provides architectural features, including predication and explicit control speculation, intended to enhance the compiler´s ability to expose instruction-level parallelism (ILP) in control-intensive programs. Aggressive structural transformations using these features, though described in the literature, have not yet been fully characterized in complete systems. Using the Intel Itanium 2 microprocessor, the SPECint2000 benchmarks and the IMPACT Compiler for IA-64, a research compiler competitive with the best commercial compilers on the platform, we provide an in situ evaluation of code generated using aggressive, EPIC-enabled techniques in a reality-constrained microarchitecture. Our work shows a 1.13 average speedup (up to 1.50) due to these compilation techniques, relative to traditionally-optimized code at the same inlining and pointer analysis levels, and a 1.55 speedup (up to 2.30) relative to GNU GCC, a solid traditional compiler. Detailed results show that the structural compilation approach provides benefits far beyond a decrease in branch misprediction penalties and that it both positively and negatively impacts instruction cache performance. We also demonstrate the increasing significance of runtime effects, such as data cache and TLB, in determining end performance and the interaction of these effects with control speculation.
Keywords
data flow analysis; instruction sets; microprocessor chips; optimising compilers; parallel architectures; performance evaluation; EPIC-enabled techniques; GNU GCC; IA-64; IMPACT EPIC research results; IMPACT compiler; Intel Itanium 2 microprocessor; Itanium 2 field-testing; SPECint2000 benchmarks; branch misprediction penalties; code optimization; computer architecture; control-intensive programs; data cache; explicitly-parallel instruction computing; inlining analysis; instruction cache performance; instruction-level parallelism; pointer analysis; reality-constrained microarchitecture; research compiler; structural transformations; Clocks; Computer aided instruction; Concurrent computing; Microarchitecture; Microprocessors; Parallel processing; Pipelines; Program processors; Runtime; Solids;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Architecture, 2004. Proceedings. 31st Annual International Symposium on
ISSN
1063-6897
Print_ISBN
0-7695-2143-6
Type
conf
DOI
10.1109/ISCA.2004.1310761
Filename
1310761
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