Variation in natural threshold voltage of NVM circuits due to dopant fluctuations and its impact on reliability

Author

Burnett, David ; Higman, J. ; Hoefler, A. ; Li, C.-N.B. ; Kuhn, P.

Author_Institution

Embedded Memory Center, Motorola, Austin, TX, USA

fYear

2002

fDate

8-11 Dec. 2002

Firstpage

529

Lastpage

532

Abstract

The statistical distribution of the natural threshold voltage (V/sub T0/) of 512k-bit NVM circuit arrays has been studied for two different technologies. The major source of the V/sub T0/ variation is dopant fluctuations of the NVM well. An analytical model for the dopant fluctuations provides excellent agreement with the measured circuit V/sub T0/ variation and NVM cell mismatch for both technologies. The reliability implications of the V/sub T0/ variation are considered using charge leakage models for data retention.

Keywords

CMOS memory circuits; cellular arrays; doping profiles; fluctuations; hot carriers; integrated circuit modelling; integrated circuit reliability; leakage currents; tunnelling; 512 kbit; NOR technology; NVM cell mismatch; NVM circuit arrays; NVM circuits; UCPE technology; analytical model; charge leakage models; data retention; dopant fluctuations; hot-carrier programming; natural threshold voltage variation; reliability; source-side Fowler-Nordheim tunneling erase; threshold voltage statistical distribution; uniform-channel-program-erase technology; Analytical models; Character generation; Circuits; Fluctuations; Histograms; Nonvolatile memory; Semiconductor device reliability; Semiconductor process modeling; Threshold voltage; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 2002. IEDM '02. International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7462-2

Type

conf

DOI

10.1109/IEDM.2002.1175896

Filename

1175896