Title :
A reduced circuit library design system
Author :
Kilmoyer, Ralph D. ; Hathaway, David J. ; Chu, Albert M.
Author_Institution :
IBM Gen. Technol. Div., Essex Junction, VT, USA
Abstract :
A reduced circuit library using triple-level metal CMOS consisting of nine primitive logic circuits and five latch kernels is proposed for a gate array library. A grouping program has been written to combine these circuits automatically into complex functions which are then hierarchically placed and wired to achieve the density and performance of a more complex library. This approach provides a set of complex functions which is optimized for each specific application while reducing the resource needed for library development and maintenance
Keywords :
CMOS integrated circuits; cellular arrays; circuit layout CAD; integrated logic circuits; ASIC; CMOS; design system; gate array library; gate arrays; grouping program; hierarchically placed; latch kernels; layout CAD; primitive logic circuits; reduced circuit library; set of complex functions; triple-level metal; Application specific integrated circuits; Capacitance; Circuit synthesis; Circuit testing; Design automation; Design optimization; Integrated circuit technology; Latches; Software libraries; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20927
