Title :
Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process
Author :
Moise, T.S. ; Summerfelt, S.R. ; McAdams, H. ; Aggarwal, S. ; Udayakumar, K.R. ; Celii, F.G. ; Martin, J.S. ; Xing, G. ; Hall, L. ; Taylor, K.J. ; Hurd, T. ; Rodriguez, J. ; Remack, K. ; Khan, M.D. ; Boku, K. ; Stacey, G. ; Yao, M. ; Albrecht, M.G. ; Ziel
Author_Institution :
Texas Instrum. Inc., Dallas, TX, USA
Abstract :
We demonstrate the bit functionality of a low-voltage, embedded ferroelectric random-access memory constructed using a 130 nm gate and five-level Cu/FSG interconnect process. By inserting the two additional masks required for the eFRAM module into this logic flow, we have co-integrated ferroelectric memory and SRAM on a single wafer.
Keywords :
CMOS memory circuits; SRAM chips; embedded systems; ferroelectric storage; integrated circuit interconnections; random-access storage; 130 nm; 130 nm five-level Cu/FSG logic process; 4 Mbit; Cu; PZT; PbZrO3TiO3; baseline CMOS technology; bit functionality; embedded FRAM; five-level Cu/FSG interconnect process; high density ferroelectric memory; integrated ferroelectric memory SRAM; logic flow; low-voltage embedded ferroelectric random-access memory; mask insertion; single wafer integration; CMOS logic circuits; Capacitors; Electrodes; Etching; Ferroelectric films; Ferroelectric materials; Instruments; Nonvolatile memory; Random access memory; Sputtering;
Conference_Titel :
Electron Devices Meeting, 2002. IEDM '02. International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7462-2
DOI :
10.1109/IEDM.2002.1175897
