Warpage and stress characteristic analyses on wire-bond-S-FCCSP structure

For the trend of electronic consumer product, more functionalities, high performance, miniaturization, high reliability and low cost have been demanded intensely, especially in the rapid growth of portable cell phone domain. Furthermore, multiple functional demand induces advanced package developments, such as system-on-chip (SoC) and System-in-Package (SiP). System-on-chip (SoC) is an ideal package to integrate multiple functionalities in the chip level. But the design and testing are not yet mature that, high cost and low manufacturing yield, drive multiple functional integration technology toward system-in-package (SiP) development. System in Package (SiP) includes technologies of Multichip Module(MCM), Multi-chip Package (MCP), stacked die, Package on Package(PoP), Package in Package (PiP) and Embedded substrate.This study is to investigate warpage, bump, low-k and solder mask stress characteristic analyses of 10 mm × 10 mm hybrid stacked-die wire-bond-S-FCCSP package by using Finite Element Method (FEM). There are several parameters to discuss in this study including die size, die thickness, substrate thickness, core thickness, mold compound thickness, mold compound material and film thickness effect to take as optimal design guidelines. In the conclusion of this study, firstly, thicker mold compound, higher CTE mold compound, smaller die size, thinner die and thicker substrate can reduce package warpage. Secondly, thinner mold compound, smaller die size and thinner die can reduce bump, low-k and S/M stresses. In summary, mold thickness and die size are the major affecting factors for all indexes.