Guarding trace and ground via-hole analysis for DDR interface designed in high-speed packages

Because of the miniaturization on the demand, the area for the layout design is decreasing. But, more and more functions are integrated. In this situation, high-speed design, for example, the DDR access interface is easy to cause simultaneous switching noises (SSN). In this paper, some analysis on this design was evaluated. The major target in our works is the DDR interface. We studied some patterns on package substrate. The major difference is the guarding traces and position of the ground via-hole. In the initial, 2D electromagnetic tool was used to estimate the amount of nets that are needed in the simulation. Inductive coupling (Lm) and capacitive coupling (Cm) are included. Then, by 3D electromagnetic tool, the circuit-model could be extracted from the 3D model. After that, spice was used for SSN simulation. In the final results, proposed solutions for the guarding nets can be reviewed. Larger inductance and coupling effects will make the signal transmission worse. Introducing guard-trace(s) can reduce these effects. Hence, improve the transmission quality. This result could be a reference for DDR interface design in high-speed application of packages.